Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 598 / 1022

Configuration Space Control and Status Registers
13-36 ADSP-BF535 Blackfin Processor Hardware Reference
PCI Configuration Header Type Register
(PCI_CFG_HT)
This register, shown in Figure 13-18 , holds the header type from the PCI
configuration registers.
The PCI core can only be single function and the configuration registers
conform to Type 0. For more information, see the PCI Local Bus Specifi-
cation Rev. 2.2.
PCI Configuration Memory Latency Timer Register
(PCI_CFG_MLT)
The
PCI_CFG_MLT
register, shown in Figure 13-19 , holds the memory
latency timer from the PCI configuration registers. It is always writable,
except where reserved, and for two hardwired bits. Write to this register
only during PCI system configuration in host mode. In device mode, the
system processor writes to this register. The lowest two bits are read only
and hardwired to 0 so that latency values are always in increments of four
PCI clock cycles.
Figure 13-18. PCI Configuration Header Type Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI Configuration Header Type Register (PCI_CFG_HT)
0000000 - Type 0
0 - Single
1 - Multifunction
Header Type[6:0] - RO
Single/Multifunction
Reset = 0x0000 0000
0xEEFF FF24