Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Architecture
1-8 ADSP-BF535 Blackfin Processor Hardware Reference
The ADSP-BF535 processor core has a dedicated low latency 64-bit wide
datapath port into the L2 SRAM memory. For example, at a core fre-
quency of 300 MHz, the peak data transfer rate across this interface is up
to 2.4 Gbytes per second.
External (Off-Chip) Memory
External memory is accessed via the External Bus Interface Unit. This
interface provides a glueless connection to up to four banks of synchro-
nous DRAM (SDRAM) as well as up to four banks of asynchronous
memory devices including flash memory, EPROM, ROM, SRAM, and
memory-mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed to inter-
face with up to four banks of SDRAM. Each bank contains between
16 Mbytes and 128 Mbytes, providing access to up to 512 Mbytes of
RAM. Each bank can be programmed independently and is contiguous
with adjacent banks, regardless of the size or placement of the banks. This
permits configuration and upgrade of the system memory, and allows the
core to view all SDRAM as a single, contiguous, physical address space.
The asynchronous memory controller can also be programmed to control
up to four banks of devices. Each bank occupies a 64 Mbyte segment
regardless of the size of the devices used, so that these banks are only con-
tiguous if fully populated with 64 Mbytes of memory.
PCI
The PCI bus defines three separate address spaces, which are accessed
through windows in the ADSP-BF535 processor memory space:
• PCI memory
• PCI I/O
• PCI configuration space