Danville Signal Processing dspstak 21262sx User Manual Download Page 1

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Danville Signal Processing, Inc.

dspstak™ 21262sx

User Manual

Version 1.10

Summary of Contents for dspstak 21262sx

Page 1: ...Danville Signal Processing Inc dspstak 21262sx User Manual Version 1 10...

Page 2: ...ice Updated operating manuals and product specification sheets are available at our website for downloading This manual may contain errors omissions or typo s Please send your comments suggestions and...

Page 3: ...mulation Port 10 dspstak 21262sx Architecture 10 Hardware ADSP 21262 Core 10 DAI 10 Parallel Port 13 SPI Port 14 Programming the dspstak 21262sx 15 Programming Modes 15 Configuration Jumpers 16 Progra...

Page 4: ...Addressing USB PLD Registers 29 PLD Output USB Status Registers 29 Memory Map 30 USB Port 30 PLD Output Registers 32 Software 34 Schematic 34 Mechanical Drawings 34 Product Warranty 35 dspstak 21262s...

Page 5: ...I O such as RS 232 and USB We currently have products based on Analog Devices SHARC processors The I O Modules may include signal conditioning electronics A D and or D A data converters audio transcei...

Page 6: ...es very flexible peripherals including six independent serial ports SPORTs and a SPI port The dspstak 21262sx Interconnect Port supports the complete DAI interface SPI general I O clocks and power con...

Page 7: ...can assume that future dspstak DSP Engines based on the 3rd generation SHARC family will support the Interconnect Port in a manner similar to the dspstak 21262sx Power Supply The dspstak 21262sx uses...

Page 8: ...maximum nominal voltage of 12VDC RS 232 Interface The RS 232 interface is used to upload user application programs and to program the clock generator in the command mode An application program may al...

Page 9: ...n the Interconnect Port The three programmable clocks on the Interconnect Port allow I O Modules to use convenient clocks for whatever devices that might be present For example an ADC might use an 18...

Page 10: ...eart of the dspstak 21262sx is an Analog Devices ADSP 21262 DSP This manual does not discuss the internal workings of this DSP the assembly language and other details specific to this DSP You should r...

Page 11: ...tal Ground Main Return 9 LED0 PLD 3 3V Digital Output 9 LED1 PLD 3 3V Digital Output 10 LED2 PLD 3 3V Digital Output 10 LED3 PLD 3 3V Digital Output 11 LED4 PLD 3 3V Digital Output 11 IO5 SPISS1 DAI 2...

Page 12: ...e Clock 28 RFS1 DAI 15 28 TFS1 DAI 16 29 RCLK1 DAI 17 29 TCLK1 DAI 18 30 RESET1 PLD 30 GND 31 DTB1 DAI 19 31 DRB1 DAI 20 32 GND 32 Vd 3 3 LEDs IO5 7 SPI_SSs DAI 1 3 Enable Resets are controlled by the...

Page 13: ...an be used to connect from a dspstak I O Module to JH2 but there is no guarantee that another dspstak DSP Engine will be compatible Samtec is a supplier for this type of connector JH2 Pinout Pin Name...

Page 14: ...tion and user EE memory It communicates over the SPI port using Flag 2 as its slave select Refer to the Peripheral Microcontroller API section of this manual for more information The SPI Port is also...

Page 15: ...programming modes are reserved for standard dspstak 21262sx functions and the remaining four are available for user programs For example you could use Mode 0 as a means to bootload one version of your...

Page 16: ...ntroller the ADSP 21262 and the Interconnect Port The Interconnect Port clocks are SYSCLK MCLK0 MCLK1 The CY22393 has three independent PLLs that allow you to generate clocks that are appropriate for...

Page 17: ...Here are the basic steps to reprogramming the CY22393 Configure the dspstak 21262sx to operate in Mode 7 M2 M1 M0 Jumpers Off Connect to an ASCII Terminal Program via RS 232 A 9 pin to 9 pin cable wit...

Page 18: ...It is still there and it loads your program but it does so silently You write your DSP applications as normal and create a ldr file Boot Type SPI Slave Format Binary Width 8 You don t really need to...

Page 19: ...boot process This will bring a new DSP prompt signifying Command Mode Type to view a list of available commands Type U to upload a new program file Your program must be a ldr ADI loader file with the...

Page 20: ...culated Type Q to quit Command Mode and the application program will boot There are a number of additional commands that are available in Command Mode For example you can read write and erase EE memor...

Page 21: ...and Summary Name Description PM_Cmd_NOP 0x00 No Operation PM_Cmd_COM_WR 0x01 Transmit a byte from the RS 232 port PM_Cmd_COM_RD 0x02 Receive a byte from the RS 232 port PM_Cmd_VERSION 0x03 Firmware ve...

Page 22: ...nless you are doing commands regularly it s best to always do a PM_Cmd_NOP before you read the status bits Status Bits Bit 0 UART RX Data Available Bit 1 UART TX Space Available Bit 2 Reserved Bit 3 R...

Page 23: ...ctive the application must ping the WD input of the Peripheral Microcontroller with a state change before the watchdog timer expires or the system will reboot The watchdog timer is initially disabled...

Page 24: ...ur program to execute different applications depending on the Mode settings For example your product might be an encoder in Mode 0 and a decoder in Mode 1 You would only need to upload one program for...

Page 25: ...y bytes at the selected baud rate You should check the UART TX Space Available Status bit in the next packet If the last byte was unsuccessfully added to the FIFO the Transmit FIFO was full the applic...

Page 26: ...sponse 0x00 This command resets the UART flushes the Transmit and Receive FIFOs and clears the UART Overrun Status bit PM_Cmd_COM_RTS_CTS Description RS 232 Handshaking Command 0x0C Data Bit 0 is CTS...

Page 27: ...hould disable writes after you are done writing the EE Memory EE_WREN is always disabled after a system reset PM_Cmd_EE_WR Description Write EE at current EE Address Command 0x06 Data EE Data Response...

Page 28: ...s Command 0x0D Data Don t Care Response EE Data EE Data is read from the current address pointed to by the EE Address Pointer This address is set by the EE_ADDR command and auto incremented after ever...

Page 29: ...H2 for external Parallel Port expansion as long as your devices are mapped into the lower half of the memory In other words AD15 must be demultiplex as either A15 or A23 0 The PLD and USB require that...

Page 30: ...rivers on our distribution CD The driver files includes dspstak inf files that are used for installation in Microsoft Windows operating systems If you are using another OS you may want to compare the...

Page 31: ...byte is available So here s the trick We address the Parallel Port to read from Address 0x8FFE You may recall that only the upper nibble is decoded by the PLD The address then auto increments to 0x900...

Page 32: ...ect lines If the pin is configured as GP I O the DAI connects to the pin as follows IO7 DAI_P1 IO6 DAI_P3 IO5 DAI_P2 PLD_OUT0 Description 3 3V Digital Output Destination Interconnect Port Address 0xB0...

Page 33: ...1 Active SPISS_MASK D12 1 Active All other bits are Don t Care This register is used for SPI slave select expansion If the mask bit is set the pin will follow the state of FLAG3 on the ADSP 21262 The...

Page 34: ...our customers through our web site Send an email to support danvillesignal com to gain access to the customer section of our web site Schematic The Distribution CD includes a schematic diagram of the...

Page 35: ...nal Processing shall at its option either repair or replace software media or firmware which do not execute their programming instructions due to such defects Danville Signal Processing does not warra...

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