USB & PLD Registers
The dspstak 21262sx uses a PLD for I/O expansion. It is connected to the DSP’s Parallel Port. The
USB port is also connected to the Parallel Port. It uses the PLD for part of its internal interface.
The Parallel Port on the ADSP-21262 has 16 multiplexed address and data lines and three control
lines, ALE, RD & WR. It can be configured as either an 8 bit bus with 24 address lines or a 16 bit
bus with 16 address lines. ALE is used as an address latch enable to demultiplex the bus.
Another characteristic of the Parallel Port is that it always wants to do 32 bit transfers. It
automatically packs and unpacks data so that from an external device point of view, an 8 bit
transfer is always 4 cycles and a 16 bit transfer is always 2 cycles. If the Parallel Port is mapped to an
external memory device such as a parallel flash memory or SRAM, this packing/unpacking feature is
quite convenient, but it creates difficulties when the target is an I/O port or FIFO.
Both the PLD and the USB port are mapped to the upper half of the Parallel Port memory. This
means that you are free to use JH2 for external Parallel Port expansion as long as your devices are
mapped into the lower half of the memory. In other words, AD15 must be demultiplex as either
A15 or A23 = 0. The PLD and USB require that the Parallel Port be configured as a 16 bit data bus,
however external devices can use either the 8 bit or 16 bit configuration.
The PLD is used to create five 4 bit wide write-only registers, demultiplex the upper AD lines, and
map the USB port to the Parallel Port. It also qualifies the RD & WR lines with A0, to deal with the
“helpful” packing/unpacking feature. The RD and WR lines are only active when A0 is low. This
means that the upper 16 bits of the 32 bit word are always ignored.
Addressing USB & PLD Registers
AD15 – AD12 (A15 – A12) are used for address decoding. Lower address bits are ignored.
PLD Output & USB Status Registers
The output registers are 4 bits wide. The D15-D12 nibble of the Parallel Port’s Transmit Buffer
Register (TXPP) is used for the data. The remaining 28 bits are ignored.
TXPP Register Format (Binary):
xxxx xxxx xxxx xxxx abcd xxxx xxxx xxxx where
x is Don’t Care and abcd represents the register.
Example: 0x0000A000 will write 0xA to the output register.
In a similar fashion, the USB Status Register should be extracted from the RXPP Register.
dspstak™ 21262sx User Manual
Page 29
