PLD_WD
Description: 3.3V Digital Output
Destination: Peripheral Microcontroller
Address: 0xE000
All data bits are Don’t Care.
A write to this register causes the Watchdog input on the Peripheral Microcontroller
to toggle. If the Watchdog Timer is enabled, you must write to this register before the
Watchdog Timer can overflow or the system will reset.
Software
The Distribution CD includes software examples that demonstrate many of the features of the
dspstak 21262sx. You may use these examples as take off points to start your own applications.
Our software library is constantly expanding. This code and other resources are available to our
customers through our web site. Send an email to
to gain access to the
customer section of our web site.
Schematic
The Distribution CD includes a schematic diagram of the dspstak 21262sx in files sa21262.pdf and
sb21262.pdf.
Mechanical Drawings
Mechanical Drawings are included in the dspstak Family Users Manual. If you any need additional
information on board mounting, clearances, etc, send an email to
.
If you are designing your own I/O Module or want to mount the dspstak 21262sx in an unusual
configuration, you may want to check with us for suggestions, design review, etc. We also have PCB
templates available to help you get started on an I/O Module layout. This will help insure that the
connectors and holes on your board actually line up.
dspstak™ 21262sx User Manual
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