Row A&C B Name
Notes
20 *
RFS0
DAI
7
20 *
TFS0
DAI
8
21 *
RCLK0
DAI
9
21 *
TCLK0
DAI
10
22 *
#RESET0 PLD
22 *
GND
23 *
DTB0
DAI
11
23 *
DRB0
DAI
12
24 *
GND
24 *
Vd+3.3
25
*
Vd+3.3
SPORT 1 – Full Duplex
25 *
GND
26 *
DRA1
DAI
13
26 *
DTA1
DAI
14
27 *
GND
27 *
MCLK1
Programmable
Clock
28 *
RFS1
DAI
15
28 *
TFS1
DAI
16
29 *
RCLK1
DAI
17
29 *
TCLK1
DAI
18
30 *
#RESET1 PLD
30 *
GND
31 *
DTB1
DAI
19
31 *
DRB1
DAI
20
32 *
GND
32 *
Vd+3.3
* LEDs, IO5-7, SPI_SSs, DAI 1-3 Enable, & Resets are controlled by the PLD Registers
Refer to the dspstak Family Users Manual for general Interconnect Port information. The USB &
PLD Register section of this manual describes the software interface to those pins mapped by the
PLD.
dspstak™ 21262sx User Manual
Page 12
