Avaya DEFINITY Server CSI, Руководство по обслуживанию, Страница: 1538 / 1930

Maintenance Objects
1538
Issue 5 October 2002
Notes:
a. The BOOTPROM Checksum Test (#80) failed. Refer to the FAIL condition
of this test for further action.
b. A parity error was detected in the processor’s data cache or instruction
cache. Aux Data indicates the difference in the number of parity errors
since the last report.
c. The Processor Bus Time-out Test (#82) failed. Refer to the FAIL condition
of this test for further action.
d. Aux Data of 100 is an LMM initialization failure.
e. The Processor Sanity Timer Test failed during a reset level 4 or 5
initialization. reset system 4 at the customers convenience and if the alarm
occurs again, replace the Processor circuit pack. The system runs with this
failure, but it is not protected if the system software has a sanity problem.
The test processor a long clear command clears this alarm, but the sanity
timer is only tested during initialization so the alarm occurs again and the
system is not protected against insane software.
1025(b) Any Processor Cache Audit
(#896) MINOR ON test processor a r 2
1281 Any Processor Cache
Test(#895) MAJOR ON test processor a r 1
1793(c) Processor Bus
Time-out Exception
Test (#82) MAJOR ON test processor a r 2
2049(d)(e
) Any Processor Sanity Timer
Test MINOR ON test processor a l c
1. The MTP Reset Test (#101) logs you off. The MTP Dual Port Ram Test (#104) can also log you off.
2. Run the Short Test Sequence first. If all tests pass, run the Long Test Sequence. Refer to the
appropriate test description and follow the recommended procedures.
Table 426. RISC Processor Circuit Pack Error Log Entries — Continued
Error
Type
Aux
Data Associated Test
Alarm
Level
On/Off
Board Test to Clear Value
1
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