Cypress S6J3200 Series, Manual

Page: 7 / 1355

Table of Contents
6 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
2. Memory Map....................................................................................................................... 246
3. FLASH Sector Configuration .............................................................................................. 246
4. Port Configuration ............................................................................................................... 246
5. Operation ............................................................................................................................ 247
5.1. Timing Chart ......................................................................................................... 247
5.2. RAM Executing Communication Protocol ............................................................. 247
5.3. Operation Flow ..................................................................................................... 251
6. Note. ................................................................................................................................... 252
6.1. PSC Port State ..................................................................................................... 252
CHAPTER 15: 12-/10-/8-bit Analog to Digital Converter .................................................................... 253
1. Overview ............................................................................................................................ 254
2. Configuration and Block Diagram ....................................................................................... 256
3. Operation of A/D Converter ................................................................................................ 257
3.1. A/D Conversion Flow ............................................................................................ 257
3.2. Logical Channel Mapping to Analog Input Signals ............................................... 259
3.3. Logical Channel Data Protection Function ........................................................... 259
3.4. Logical Channel Triggering and Priority ................................................................ 261
3.5. Group Processing ................................................................................................. 263
3.6. Multiple Conversion Logical Channels .................................................................. 271
3.7. Forced Stop .......................................................................................................... 274
3.8. A/D Converter Calibration ..................................................................................... 275
3.9. DMA Transfer Function ......................................................................................... 277
3.10. Range Comparator Function ................................................................................ 277
3.11. Pulse Detection Function ...................................................................................... 280
3.12. Debug Mode ......................................................................................................... 282
4. Setup Procedure Examples ................................................................................................ 283
4.1. Control of A/D Conversion .................................................................................... 283
4.2. Setting of Global A/D Conversion ......................................................................... 284
4.3. Setting of Logical Channel .................................................................................... 285
4.4. Setting of Range Comparator ............................................................................... 286
4.5. Setting of Pulse Detection .................................................................................... 287
4.6. A/D Conversion .................................................................................................... 288
4.7. Range Comparator ............................................................................................... 290
4.8. Pulse Detection .................................................................................................... 291
5. Registers ............................................................................................................................ 292
5.1. A/D Channel Control Registers (ADC12Bn_CHCTRL0 to 63) .............................. 293
5.2. A/D Channel Status Registers (ADC12Bn_CHSTAT0 to 63) ................................ 297
5.3. A/D Conversion Data Registers (ADC12Bn_CD0 to 63) ...................................... 299
5.4. Pulse Counter Control Registers (ADC12Bn_PCCTRL0 to 63) ............................ 301
5.5. A/D Conversion Done Interrupt Flag Registers (ADC12Bn_CDONEIRQ0 to 1) ... 303
5.6. A/D Conversion Done Interrupt Enable Registers (ADC12Bn_CDONEIRQE0 to
1) .......................................................................................................................... 306
5.7. A/D Conversion Done Interrupt Clear Registers (ADC12Bn_CDONEIRQC0 to 1)309
5.8. Group Interrupted Interrupt Flag Registers (ADC12Bn_GRPIRQ0 to 1) ............... 312
5.9. Group Interrupted Interrupt Enable Registers (ADC12Bn_GRPIRQE0 to 1) ........ 315
5.10. Group Interrupted Interrupt Clear Registers (ADC12Bn_GRPIRQC0 to 1) .......... 317
5.11. Range Comparator Interrupt Flag Registers (ADC12Bn_RCIRQ0 to 1) ............... 319
5.12. Range Comparator Interrupt Enable Registers (ADC12Bn_RCIRQE0 to 1) ........ 323