Cypress S6J3200 Series, Manual

Page: 413 / 1355

CHAPTER 18:Sound Generator
412 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.1.
Relation between the Amplitude Data Register (SGAR) and PWM Pulse
This section describes the relation between the Amplitude Data Register (SGAR) and a PWM pulse.
Figure 3
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2 The Relation between the Amplitude Data Register (SGAR) and PWM Pulse
The amplitude data is output as a PWM (Pulse Width Modulation) waveform on the SGA pin.
The length of a PWM cycle is programmable in the PWM Cycle Data Register (SGPCR). This length is
based on the count of input clock. The initial value is 256 input clock cycle (SGPCR=0x00FF).
The value [Amplitude Data Register (SGAR) + 1] means the number of input clock cycles in which the
SGA pin is "H" during 1 PWM cycle. Moreover, when the Amplitude Data Register (SGAR) is greater than
or equal to the PWM Cycle Data Register (SGPCR), the SGA pin output is always "H".
SGAR
0x0000
0x0080
0x00FE
0x00FF
1 PWM cycle
(256 input clock cycles)
(1 input clock cycle)
(129 input clock cycles)
(255 input clock cycles)
all "H"
1 PWM cycle
(256 input clock cycles)