Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
638 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.7.
TX Buffer Queue Base Address Register (ETHERNETn_transmit_q_ptr)
This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The TX
Buffer Queue Base Address register must be initialized before transmit is started through bit 9 of the
Network Control register. Once transmission has started, any write to the TX Buffer Queue Base Address
register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a
maximum of four clock cycles from the writing of the transmit start bit before the transmitter is active.
Writing to the TX Buffer Queue Base Address register during this time may produce unpredictable results.
Reading this register returns the location of the descriptor currently being accessed. Since the Ethernet
MAC DMA handles two frames at once, this may not necessarily be pointing to the current frame being
transmitted. In terms of AMBA AXI operation, the transmit descriptors are written to memory using a
single 32-bit AXI access. Since the datapath is 64-bit wide, the transmit descriptors shall be aligned at
64-bit boundaries and each pair of 32-bit descriptors is read from memory using a single 64-bit AXI
access.
REGISTER_NAME ETHERNETn_transmit_q_ptr
OFFSET 0x01C
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME dma_tx_q_ptr[31:24]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME dma_tx_q_ptr[23:16]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME dma_tx_q_ptr[15:8]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME dma_tx_q_ptr[7:2] Reserved
ACCESS_TYPE R/W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00 0x0