Cypress S6J3200 Series, Manual

Page: 446 / 1355

CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 445
[bit4] NRE : Tone output number update enable bit
This bit is to enable the update of the tone output number of the Tone Output Number Register (SGNR)
through the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the tone output number is disabled.
1 The update of the tone output number is enabled.
[bit3] TCRE : Time cycle update enable bit
This bit is to enable the update of the time cycle of the Time Cycle Register (SGTCR) through the DMA
Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the time cycle is disabled.
1 The update of the time cycle is enabled.
[bit2] IDRE : Increase and decrease data update enable bit
This bit is to enable the update of the increase and decrease data of the Increase and Decrease Data
Register (SGIDR) through the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the increase and decrease data is disabled.
1 The update of the increase and decrease data is enabled.
[bit1] PCRE1 : PWM cycle data (upper byte) update enable bit
This bit is to enable the update of the PWM cycle data (upper byte) of the PWM Cycle Data Register
(SGPCR) through the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the PWM cycle data (upper byte) is disabled.
1 The update of the PWM cycle data (upper byte) is enabled.
[bit0] PCRE0 : PWM cycle data (lower byte) update enable bit
This bit is to enable the update of the PWM cycle data (lower byte) of the PWM Cycle Data Register
(SGPCR) through the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the PWM cycle data (lower byte) is disabled.
1 The update of the PWM cycle data (lower byte) is enabled.