Cypress S6J3200 Series, Manual

Page: 1173 / 1355

CHAPTER 32:Memory Protection Unit for AHB
1172 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bit Position Bit Field Name Bit Description
[12] PROT
Privileged Mode Attribute When the privileged mode overwrite feature is
available and POEN = "1", the privilege attribute on AHB memory interface is
controlled by this bit.
"0": Non-privileged mode
"1": Privileged mode
[11] POEN
Privileged Mode Overwrite Feature Enable
"0": Privileged mode overwrite feature is disabled
"1": Privileged mode overwrite feature is enabled
Note: For availability of the privileged mode overwrite feature, refer to the
device-specific datasheet.
[10] MPUSTOPEN
Enable for MPU STOP Feature
"0": MPU STOP feature is disabled
"1": MPU STOP feature is enabled
This bit together with MPU STOP input controls the STOP status of MPU
AHB.
[9] MPUSTOP
MPU STOP Status
"0": MPU AHB is not in STOP mode
"1": MPU AHB is in STOP mode (i.e. MPUSTOPEN = "1" and MPU STOP
input is asserted). All accesses are blocked in this mode
Note: For availability of the MPU STOP feature, refer to the device specific
datasheet.
[8] LST
MPU Lock Status
"0": MPU AHB is unlocked; registers in MPU AHB can be written
"1": MPU AHB is locked; no registers (other than MPUHn_UNLOCK register)
in MPU AHB can be written
[7:2] read0
-
[1] NMICL
NMI Interrupt Clear
"0": No effect
"1": Clears the NMI interrupt flag
Read returns "0".
[0] NMI
NMI Interrupt Flag
This interrupt flag indicates that the memory protection violation was detected
for an AHB transfer.
Note:
−
The register bits MPUHn_CTRL0:AP[2:0], MPUHn_CTRL0:MPUSTOPEN,
MPUHm_CTRL0:POEN and MPUHn_CTRL0:PROT can only be written when the MPU is
disabled (MPUHn_CTRL0:MPUEN = "0").