Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
592 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
passed onto the Ethernet MAC registers. If the frame has a good status, the information is used to read
the frame from the RX Packet Buffer Memory and burst onto the AXI Master Interface using the DMA
buffer management protocol.
If partial store and forward mode is active, the RX DMA will begin fetching the packet data before the
status is available. As soon as the status becomes available, the RX DMA will fetch this information
before continuing to fetch the remainder of the frame.
3.1.8.
Priority Queuing in the Ethernet MAC DMA
The Ethernet MAC DMA uses 4 transmit and 4 receive queues. Each queue has an independent list of
buffer descriptors pointing to separate data streams.
In the transmit direction, higher priority queues are serviced before lower priority queues.
This strict priority scheme requires the user to ensure that high priority traffic is constrained such that
lower priority traffic will have the required bandwidth.
The Ethernet MAC DMA will determine the next queue to service by initiating a sequence of buffer
descriptor reads interrogating the ownership bits of each. The buffer descriptor corresponding to the
highest priority queue is read first. If the ownership bit of this descriptor is “1”, then the Ethernet MAC
DMA will progress to reading the 2
nd
highest priority queue’s descriptor. If that ownership bit read of this
lower priority queue is “1”, then the Ethernet MAC DMA will read the 3 rd highest priority queue’s descriptor,
and so on. If all the descriptors return an ownership bit set, then a resource error has occurred, an
interrupt is generated and transmission is automatically halted.
Transmission can only be restarted by setting the start bit (tx_start_clk) in the Network Control register
(ETHERNETn_network_control[9]). The Ethernet MAC DMA will need to identify the highest available
queue for transmit from when the start bit in the Network Control register is written to and the TX is in a
halted state, or when the last word of any packet has been fetched from system memory.
The Ethernet MAC TX DMA will maximize the effectiveness of priority queuing by ensuring that high
priority traffic be transmitted as early as possible after being fetched from system memory. High priority
traffic will be pushed to the MAC layer depending on traffic shaping being enabled and the associated
credit value for that queue, before any lower priority traffic that may pre-exist in the TX Packet Buffer. This
is achieved by separating the TX Packet Buffer Memory into regions, 4 regions per queue. The size of
each region determines the amount of memory space allocated per queue and is 1Kbytes per region.
If a higher priority transmit queue contains relatively longer buffer, it can happen that a shorter frame from
a lower priority queue is transferred before the higher prority queue.For each queue, there is an
associated transmit buffer queue base address register. For the lowest priority queue (Queue 0), the TX
Buffer Queue Base Address register is located at offset address 0x01C. For queues 1 to 3 the transmit
buffer queue base address registers are located at sequential offset addresses starting at 0x440.
In the receive direction each data packet is written to system memory in the order that it is received. For
each queue, there is an independent set of receive buffers for each queue. For each queue, there is an
associated receive buffer queue base address register. For the lowest priority queue (Queue 0), the RX
Buffer Queue Base Address register is located at offset address 0x018. For queues 1 to 3 the receive
buffer queue base address registers are located at sequential offset addresses starting at 0x480. Every
received packet will pass through a programmable screening algorithm which will allocate to that frame a