Cypress S6J3200 Series, Manual

Page: 418 / 1355

CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 417
The table below shows the relations between
"the setting of the DMA Transfer Update Enable Register (SGDER)"
and
"the byte position in the DMA Transfer Intermediate Register (SGDMAR)".
The byte position in the DMA Transfer Intermediate Register (SGDMAR) corresponds to the selection of
the following registers.
-
Time Cycle Register (SGTCR[7:0])
-
Increase and Decrease Data Register (SGIDR[7:0])
-
PWM Cycle Data Register (SGPCR[15:0])
The transfer size #2 is calculated by the setting of {SGDER.TCRE, SGDER.IDRE, SGDER.PCRE1, and
SGDER.PCRE0} in the DMA Transfer Update Enable Register (SGDER). When this transfer size #2 is
not 4 bytes, the transfer byte position is left-aligned.
Table 3-2 The Relations between the Setting of the DMA Transfer Update Enable Register (SGDER) and Transfer
Byte Position of SGDMAR #2
No.
Setting of SGDER
Transfer
Size #2
*1
Transfer Byte Position of SGDMAR
TCRE IDRE PCRE1 PCRE0
SGTCR
[7:0]
SGIDR
[7:0]
SGPCR
[15:8]
SGPCR
[7:0]
1 0 0 0 0 0
- - - -
2 1 0 0 0 1
SGDMAR
[31:24]
- - -
3 0 1 0 0 1
-
SGDMAR
[31:24]
- -
4 1 1 0 0 2
SGDMAR
[31:24]
SGDMAR
[23:16]
- -
5 0 0 1 0 1
- -
SGDMAR
[31:24]
-
6 1 0 1 0 2
SGDMAR
[31:24]
-
SGDMAR
[23:16]
-
7 0 1 1 0 2
-
SGDMAR
[31:24]
SGDMAR
[23:16]
-
8 1 1 1 0 4
SGDMAR
[31:24]
SGDMAR
[23:16]
SGDMAR
[15:8]
-
9 0 0 0 1 1
- - -
SGDMAR
[31:24]
10 1 0 0 1 2
SGDMAR
[31:24]
- -
SGDMAR
[23:16]
11 0 1 0 1 2
-
SGDMAR
[31:24]
-
SGDMAR
[23:16]
12 1 1 0 1 4
SGDMAR
[31:24]
SGDMAR
[23:16]
-
SGDMAR
[15:8]
13 0 0 1 1 2
- -
SGDMAR
[31:24]
SGDMAR
[23:16]