Cypress S6J3200 Series, Manual

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CHAPTER 28:LCD Controller
1060 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
6.5.
LCDC Static Control Register: LCRS
The bit configuration of the LCDC static control register is shown below.

LCRS
bit
7 6 5 4 3 2 1 0
Field
SCSS LCSEN LCS3 LCS2 LCS1 LCS0 FPS1 FPS0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Protection
attribute
- - - - - - - -
Initial value 0 0 0 0 0 0 0 0
[bit7] SCSS: Frame cycle generation clock for static drive selection bit
Bit Operation
0 Main clock
1 Sub clock
For the single clock products, set "0".
[bit6] LCSEN: PSS Timer mode (main oscillation operation / sub oscillation operation)
operation enable
Bit Operation
0
LCD display stop in the PSS timer mode(main oscillation operation/ sub
oscillation operation)
1
LCD display in the PSS timer mode(main oscillation operation/ sub oscillation
operation)
When LCSEN="1", please do not stop the clock oscillation which selected by the SCSS bit during the
transition to PSS mode.
LCD display stop when power shutdown.
[bit5:2] LCS3 to LCS0: Static drive selection
LCS3 LCS2 LCS1 LCS0
Static Drive Selection Port
Common / Segment Output
0 0 0 0 OFF
0 0 0 1 ST0, ST1