Cypress S6J3200 Series, Manual

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CHAPTER 27:HyperBus Interface
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1009
Figure 3-2 Write Waveform
CA0
47-40
CA0
39-32
CA1
31-24
CA1
23-16
CA0
15-8 CA0
7-0
Dn
7-0
Dn
15-8
Dn+1
7-0
Dn+1
15-8
Dn+x
7-0
Dn+x
15-8
CSn
CK
RWDS
DQ[7:0]
3.1.3.
Write Operation with Byte Mask
This section describes the write operation of HYPERBUSI with byte mask for HyperRAM. HYPERBUSI
asserts CSn, CK, and DQ. Then, it outputs 3 words command/address, and writes 1 or more data after
latency cycles. This write operation is used when the DEVTYPE of HYPERBUSI_MCRn is chosen as
HyperRAM. The HYPERBUSI module outputs RWDS signal as the byte mask during write operation. The
invalid write data is masked by high of RWDS.
The HYPERBUSI module puts the transaction request from AXI bus, such as the burst type and the burst
length, to the C/A cycle on HyperBus as is. Therefore, RWDS is determined by the access address, data
size, and strobe signal on AXI bus.
Figure 3-3 Write Waveform with Byte Mask
CA0
47-40
CA0
39-32
CA1
31-24
CA1
23-16
CA0
15-8 CA0
7-0
Dn
7-0
Dn
15-8
Dn+1
7-0
Dn+1
15-8
CSn
CK
RWDS
DQ[7:0]
Note:
−
In Figure 3-3, Dn 15-8 and Dn+1 7-0 are invalid data.
3.1.4.
Timing Adjustment
This section describes the HyperBus timing adjustment. HyperBus core has timing adjustment circuit and
timing adjustment is controlled by HYPERBUSI_MTRn. RCSHI, RCSS, and RCSH in
HYPERBUSI_MTRn are used for the read timing adjustment, and WCSHI, WCSS, and WCSH in
HYPERBUSI_MTRn are used for the write timing adjustment. Please refer to section 4.6 Memory Timing
Register (HYPERBUSIn_MTR0 to 1).