CHAPTER 5:Clock Configuration
58
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Source Clock
System
Clock Name
Function
Local clock
name
Description
SSCG3
CLK_CD1
Hyperbus Interface (MCU)
No Define
External Clock for HyperBus memory
interface
SSCG3
CLK_CD1
Hyperbus Interface (GDC)
No Define
External Clock for HyperBus memory
interface
Sub clock
Sub Clock
LCD Controller
Sub clock
-
Notes:
−
The configuration of the maximum clock frequency above should satisfy the values specified in
Datasheet.
−
The frequency of CLK_CD5 and CLK_CD5A0 should satisfy the following conditions.
➢
CLK_CD5 = 240MHz or 120MHz.
➢
CLK_CD5A0 = 120MHz.
−
Read/Write access from CPU or DMA may bring about dead-lock when the clock source is not
supplied to the accessed clock domain because "handshake" for AXI transaction cannot be done.
If you want to quit a clock generation for some clock domain, you also need to configure an
access protection for the domain using MPU.
Summary of Contents for S6J3200 Series
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