CHAPTER 26:PCMPWM
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
1001
4.7.
PCM Interrupt Status Register (PCMPWMi_INTRSTAT)
This PCM Interrupt Status Register reflects the status of the individual interrupt sources of the PCMPWM
module. The bits in this registers are "sticky", i.e. once they have been set from the hardware, they
remain set until they are reset via a write access to the PCMPWMi_INTRCLR register.
REGISTER_NAME
PCMPWMi_INTRSTAT
OFFSET
0x00000018
ACCESS_SIZE
B, H, W
MULTIPLE
0
NUMERIC_TYPE
-
OTHER
-
BIT_OFFSET
31
30
29
28
27
26
25
24
BIT_NAME
Reserved
ACCESS_TYPE
R0,WN
PROT_TYPE
WN
INITIAL_VALUE
0
BIT_OFFSET
23
22
21
20
19
18
17
16
BIT_NAME
Reserved
ACCESS_TYPE
R0,WN
PROT_TYPE
WN
INITIAL_VALUE
0
BIT_OFFSET
15
14
13
12
11
10
9
8
BIT_NAME
Reserved
ACCESS_TYPE
R0,WN
PROT_TYPE
WN
INITIAL_VALUE
0
BIT_OFFSET
7
6
5
4
3
2
1
0
BIT_NAME
Reserved
DMA_ERR
UDRN
OVFL
DREQ
ACCESS_TYPE
R0,WN
R,WN
R,WN
R,WN
R,WN
PROT_TYPE
WN
INITIAL_VALUE
0
0
0
0
0
Summary of Contents for S6J3200 Series
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