Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 717
4.62.
Octets Receive TOP Register (ETHERNETn_octets_rxed_top)
Description of Octets Receive [47:32] register is shown. When reading the Octets Receive registers, bits
[31:0] (ETHERNETn_octets_rxed_bottom) should be read prior to bits [47:32]
(ETHERNETn_octets_rxed_top) to ensure reliable operation.
REGISTER_NAME ETHERNETn_octets_rxed_top
OFFSET 0x154
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME count[47:40]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME count[39:32]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:16] Reserved
Always read "0". Writing has no effect.
[bit15:0] count: Transmitted octets in frame without errors [47:32]
The number of octets received in valid frames of any type. This counter is 48-bits, and is read through
two registers (ETHERNETn_octets_rxed_top and ETHERNETn_octets_rxed_bottom). This count does
not include octets from pause frames, and is only incremented if the frame is successfully filtered and
copied to memory.