Cypress S6J3200 Series, Manual

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CHAPTER 25:Programmable CRC
972 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit15:12] read0 : -
[bit11] RIBIT : Reflect Input Bits
Bit Description
0 Disable input bit reflection
1 Enable input bit reflection
When the input data in the CRCn_WR register is passed to the CRC engine, the bit ordering of each
byte within input data is reversed. For more details refer to Section "Operation of the Programmable
CRC".
[bit10] RIBYT : Reflect Input Bytes
Bit Description
0 Disable input byte reflection (swapping)
1 Enable input byte reflection (swapping)
When the input data in the CRCn_WR register is passed to the CRC engine, the byte ordering of input
data is reversed. Only the bytes of the configured input data size CRCn_CFG:SZ are affected. For
more details refer to Section "Operation of the Programmable CRC".
Note:
−
For 8-bit input data, this setting has no effect.
[bit9] ROBIT : Reflect Output Bits
Bit Description
0 Disable output bit reflection
1 Enable output bit reflection
The bit ordering of each byte within checksum is reversed, before passing the checksum to final
XOR'ing stage. For more details refer to Section "Operation of the Programmable CRC".
[bit8] ROBYT : Reflect Output Bytes
Bit Description
0 Disable output byte reflection (swapping)
1 Enable output byte reflection (swapping)
The byte ordering of checksum data is reversed, before passing the byte aligned polynomial length of
checksum data to final XOR'ing stage. For more details refer to Section "Operation of the
Programmable CRC".
Note:
−
For the checksum data less than or equal to 8 bits, this setting has no effect.
[bit7:1] read0 : -
[bit0] CIRQCLR : Interrupt Clear
This bit clears the CRC interrupt flag.
Bit Description
0 Write "0" is ignored, reading this bit always returns "0"
1 Clear CRC interrupt flag (CRCn_CFG:CIRQ)