Cypress S6J3200 Series, Manual

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Table of Contents
16 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
CHAPTER 25: Programmable CRC ................................................................................................... 956
1. Overview ............................................................................................................................ 957
2. Configuration and Block Diagram ....................................................................................... 958
3. Operation of the Programmable CRC ................................................................................. 958
3.1. CRC Operation Flowcharts ................................................................................... 958
3.2. CRC Input Data and Checksum Calculation Flow ................................................ 962
3.3. CRC Calculation Example .................................................................................... 965
4. Registers ............................................................................................................................ 966
4.1. CRC Polynomial Register (CRCn_POLY)............................................................. 967
4.2. CRC Seed Register (CRCn_SEED) ..................................................................... 968
4.3. CRC Final XOR Register (CRCn_FXOR) ............................................................. 969
4.4. CRC Configuration Register (CRCn_CFG) .......................................................... 970
4.5. CRC Write Register (CRCn_WR) ......................................................................... 973
4.6. CRC Read Register (CRCn_RD).......................................................................... 974
CHAPTER 26: PCMPWM .................................................................................................................. 975
1. Overview ............................................................................................................................ 976
2. Configuration and Block Diagram ....................................................................................... 977
2.1. Block Diagram ...................................................................................................... 977
2.2. Configuration of the PCMPWM Module ................................................................ 978
2.3. Output Configuration ............................................................................................ 982
3. Operation of the PCMPWM ................................................................................................ 983
3.1. Description of the PCM to PWM Conversion Process .......................................... 983
3.2. PWM Cycle Time Configuration ............................................................................ 988
3.3. PCM Data Sample Input ....................................................................................... 988
3.4. Interrupts .............................................................................................................. 989
3.5. Dead Timer Operation .......................................................................................... 989
4. Registers ............................................................................................................................ 990
4.1. PCMPWM Control Register (PCMPWMi_CONTROL) .......................................... 991
4.2. PCMPWM Output Control Register (PCMPWMi_OCTRL) ................................... 994
4.3. PCMPWM Clock Select Register (PCMPWMi_CLKSEL) ..................................... 996
4.4. PCMPWM Count Period Register (PCMPWMi_COUNTP) ................................... 997
4.5. PCM Offset Register (PCMPWMi_PCMOFFS) .................................................... 998
4.6. PCM Interrupt Enable Register (PCMPWMi_INTREN) ......................................... 999
4.7. PCM Interrupt Status Register (PCMPWMi_INTRSTAT) .................................... 1001
4.8. PCM Interrupt Clear Register (PCMPWMi_INTRCLR) ....................................... 1003
4.9. PCM Data Register 0..15 (PCMPWMi_DATA) .................................................... 1005
CHAPTER 27: HyperBus Interface .................................................................................................. 1006
1. Overview .......................................................................................................................... 1007
2. Block Diagram .................................................................................................................. 1007
3. Operation of the HYPERBUSI .......................................................................................... 1008
3.1. HyperBus Core ................................................................................................... 1008
3.2. Tx/Rx Controller.................................................................................................. 1011
3.3. C/A Coder ........................................................................................................... 1012
3.4. FIFO ................................................................................................................... 1013
3.5. CS REG (Control Status Register) ..................................................................... 1014
3.6. AXI Slave Interface ............................................................................................. 1015
4. Registers .......................................................................................................................... 1016
4.1. Controller Status Register (HYPERBUSIn_CSR) ............................................... 1017