Cypress S6J3200 Series, Manual

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CHAPTER 29:Indicator PWM
1112 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.6.
PWM Cycle Setting Register (IPCSR)
The PWM cycle setting register (IPCSR) is a register with a buffer for setting a cycle. Transfer to the timer
is performed upon software trigger activation. Note that rewriting is not supported while a timer count
operation is in progress (ICNTCR:DOP[bit]=1).
REGISTER_NAME IPCSR
OFFSET 0x00
ACCESS_SIZE B H W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME IPCSR[15] IPCSR[14] IPCSR[13] IPCSR[12] IPCSR[11] IPCSR[10] IPCSR[9] IPCSR[8]
ACCESS_TYPE R,W R,W R,W R,W R,W R,W R,W R,W
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME IPCSR[7] IPCSR[6] IPCSR[5] IPCSR[4] IPCSR[3] IPCSR[2] IPCSR[1] IPCSR[0]
ACCESS_TYPE R,W R,W R,W R,W R,W R,W R,W R,W
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:16] Reserved
These are reserved bits. Writing data to these bits has no effect on operation.
[bit15:0] IPCSR: PWM cycle setting register
This register is for setting the PWM timer cycle. Transfer to the timer is performed upon software trigger
activation.
Stop the timer (ICNTCR:DOP[bit]=0) before configuring the PWM cycle setting register (IPCSR) setting.
Settings are ignored if they are configured while timer operation is in progress (ICNTCR:DOP[bit]=1).