CHAPTER 21:Ethernet MAC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit3:0] mask_enable: Data Buffer Address Mask Enable
These bits are associated directly with bits [31:28].When bit 0 is set, the AXI address bit 28 used for
accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1
is set, the AXI address bit 29 used for accessing the receive data buffers will be forced to the value
stored in bit 29 of this register. When bit 2 is set, the AXI address bit 30 used for accessing the receive
data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI address
bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this
register. When these bits are clear, the associated value stored in bits [31:28] have no effect on the AXI
address used for receive data buffer accesses. Any changes to this register will be ignored while the
DMA is currently processing a receive packet. It will only affect the next full packet to be written to
system memory.
Summary of Contents for S6J3200 Series
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