Cypress S6J3200 Series, Manual

Page: 615 / 1355

CHAPTER 21:Ethernet MAC
614 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
TCP Checksum Errors Register (ETHERNETn_rx_tcp_ck_errors)
UDP Checksum Errors Register (ETHERNETn_rx_udp_ck_errors)
Receive DMA Flushed Packets Register (ETHERNETn_auto_flushed_pkts)
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end of statistics registers
IEEE 1588 Timer Increment Sub Nanoseconds Register (ETHERNETn_tsu_timer_incr_sub_nsec)
IEEE 1588 Timer Seconds [47:32] Register (ETHERNETn_tsu_timer_msb_sec)
IEEE 1588 Timer Seconds [31:0] Register (ETHERNETn_tsu_timer_sec)
IEEE 1588 Timer Nanoseconds Register (ETHERNETn_tsu_timer_nsec)
IEEE 1588 Timer Adjust Register (ETHERNETn_tsu_timer_adjust)
IEEE 1588 Timer Increment Register (ETHERNETn_tsu_timer_incr)
PTP Event Frame Transmitted Seconds [31:0] Register (ETHERNETn_tsu_ptp_tx_sec)
PTP Event Frame Transmitted Nanoseconds Register (ETHERNETn_tsu_ptp_tx_nsec)
PTP Event Frame Received Seconds [31:0] Register (ETHERNETn_tsu_ptp_rx_sec)
PTP Event Frame Received Nanoseconds Register (ETHERNETn_tsu_ptp_rx_nsec)
PTP Peer Event Frame Transmitted Seconds [31:0] Register (ETHERNETn_tsu_peer_tx_sec)
PTP Peer Event Frame Transmitted Nanoseconds Register (ETHERNETn_tsu_peer_tx_nsec)
PTP Peer Event Frame Received Seconds [31:0] Register (ETHERNETn_tsu_peer_rx_sec)
PTP Peer Event Frame Received Nanoseconds Register (ETHERNETn_tsu_peer_rx_nsec)
Receive LPI Transitions Register (ETHERNETn_rx_lpi)
Received LPI Time Register (ETHERNETn_rx_lpi_time)
Transmit LPI Transitions Register (ETHERNETn_tx_lpi)
Transmit LPI Time Register (ETHERNETn_tx_lpi_time)
Interrupt Status Queue 1 Status Register (ETHERNETn_int_status_q1)
Interrupt Status Queue 2 Status Register (ETHERNETn_int_status_q2)
Interrupt Status Queue 3 Status Register (ETHERNETn_int_status_q3)
TX Buffer Queue 1 Base Address Register (ETHERNETn_transmit_q1_ptr)
TX Buffer Queue 2 Base Address Register (ETHERNETn_transmit_q2_ptr)
TX Buffer Queue 3 Base Address Register (ETHERNETn_transmit_q3_ptr)
RX Buffer Queue 1 Base Address Register (ETHERNETn_receive_q1_ptr)
RX Buffer Queue 2 Base Address Register (ETHERNETn_receive_q2_ptr)
RX Buffer Queue 3 Base Address Register (ETHERNETn_receive_q3_ptr)
RX Buffer Size Queue 1 Register (ETHERNETn_rxbuf_size_q1)
RX Buffer Size Queue 2 Register (ETHERNETn_rxbuf_size_q2)
RX Buffer Size Queue 3 Register (ETHERNETn_rxbuf_size_q3)
CBS Control Register (ETHERNETn_cbs_control)
CBS IdleSlope Queue A Register (ETHERNETn_cbs_idleslope_q_a)
CBS IdleSlope Queue B Register (ETHERNETn_cbs_idleslope_q_b)