CHAPTER 21:Ethernet MAC
682
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.29.
Specific Address Mask 1 Top Register
Description of Specific Address Mask 1 Top register is shown.
REGISTER_NAME
ETHERNETn_mask_add1_top
OFFSET
0x0CC
ACCESS_SIZE
W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET
31
30
29
28
27
26
25
24
BIT_NAME
Reserved
ACCESS_TYPE
R0,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
23
22
21
20
19
18
17
16
BIT_NAME
Reserved
ACCESS_TYPE
R0,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
15
14
13
12
11
10
9
8
BIT_NAME
address_mask[47:40]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
7
6
5
4
3
2
1
0
BIT_NAME
address_mask[39:32]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
[bit31:16] Reserved
Always read "0". Writing has no effect.
[bit15:0] address_mask: Specific Address Mask [47:32]
Setting a bit to "1" masks the corresponding bit in the Specific Address Top i register.
Summary of Contents for S6J3200 Series
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