Cypress S6J3200 Series, Manual, Page: 827 / 1355

CHAPTER 22:Media Local Bus Interface (MediaLB)
826 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
MediaLB DIM
The function block of MediaLB is provided by SMSC IP OS62400 MediaLB Device Interface Macro. It
implements the Physical and Link Layer requirements outlined in the MediaLB Specification by SMSC
(TB0400AN3V0, rev 3.0 issued on February 2006).
Local Channel Buffer (SRAM)
A 9kbit SRAM is used for buffering of logical channel data for compensating the bus latency. It stores up
to 256 quadlets plus tag information (256 words x 36 bits).
1. AHB Master Interface
The AHB Master Interface allows the MediaLB to access the system memory. It converts the MediaLB
Host Bus Interface (HBI) protocol to AHB protocol.
2. AHB Slave Interface
The AHB Master Interface allows the bus masters to access the MediaLB configuration and status
registers. It converts the AHB protocol to MediaLB Peripheral Bus Interface (PBI).
Notes:
−
In devices that use MediaLB, a minimum PERI4 clock value is specified. Please refer to the
Internal Clock Timing table in the device-specific datasheet.
−
In addition, the system must be able to handle 6 MByte/sec on the bus. This means that,
depending on the bus traffic as well as access to system RAM by other masters, higher PERI4
clock frequencies are recommended.
MediaLB IO Mode
The IO mode dictates a particular method used for transferring data between the local channel buffer and
the system memory. For channels configured to receive data from the MediaLB interface, system
software is responsible for periodically unloading RX data from the local channel buffer. For channels
configured to transmit data to the MediaLB Interface, system software is responsible for periodically
loading the local channel buffer with TX data. The MLBn_CCBCRn and MLBn_CNBCRn registers,
accessed through the AHB Slave interface, are used as a data receive buffer and a data transmit buffer,
respectively.
For details on the IO Mode operation, please contact SMSC.
MediaLB DMA Mode
The DMA mode is a mode in which MediaLB accesses the system memory via the AHB Master bus. The
system memory contains transmitted and received data, which can be read by software and the MediaLB.
When MediaLB is used in the DMA mode, data is transmitted and received via the system memory. When
used in the DMA mode, MediaLB functions as a master of the AHB bus, reading and writing data from and
to the system memory. When MediaLB accesses the AHB bus, Buffer Current Address BCA[15:0] in
Channel n Current Buffer Configuration Register (MLBn_CCBCRn) for MediaLB is output as the address
of the AHB bus. In the DMA mode, two types of buffering is supported: Ping-Pong and circular buffering.