Cypress S6J3200 Series, Manual

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CHAPTER 27:HyperBus Interface
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1011
3.2.
Tx/Rx Controller
This section describes the Tx/Rx Controller of HYPERBUSI module. The Tx/Rx Controller performs
Tx/Rx operation control by state machine, and flow control of data between AXI bus and HyperBus. In
addition, when next access address is accepted by multiple outstanding address on AXI bus,
HYPERBUSI passes the transaction to the Continuous Read Ctrl if the address of subsequent access is
continuous address to the present access.
3.2.1.
Asymmetry Cache System Support
This section describes the asymmetry cache system support. The Tx/Rx Controller supports the system
which has a different request size of the wrap burst from asymmetry cache system by having wrap size
setting of HyperBus memory. This function is optional. Please refer to 4.5 Memory Configuration Register
(HYPERBUSIn_MCR0 to 1) for more detailed information.
The operation of the Tx/Rx Controller for asymmetry cache system support is below.
−
The Tx/Rx Controller accepts the wrap read transaction, and compares the required wrap size with
the WRAPSIZE in HYPERBUSI_MCRn.
−
When the wrap size is the same, the Tx/Rx Controller requires the wrap burst read to the HyperBus.
−
When the wrap size differs, the Tx/Rx Controller emulates wrap burst read by requesting two
continuous burst read to the HyperBus.
3.2.2.
Continuous Read Ctrl
This section describes the Continuous Read Ctrl of HYPERBUSI module. When the address of
subsequent access is continuous address to the present access, Continuous Read Ctrl merges the
subsequent access to present access in order to improve the performance by removing the C/A cycle and
initial latency cycle.
The Continuous Read Ctrl merges some read transactions by the following condition.
−
Access to HyperFlash.
−
Between the sequential read transactions which have INCR as the type of the burst and have the
continuous address on AXI bus are merged.
−
Between the read transaction with WRAP and the subsequent read transaction with INCR which
have an address following the final address of wrap boundary are merged. This function is optional.
Please refer to 4.5 Memory Configuration Register (HYPERBUSIn_MCR0 to 1) for more detailed
information.