CHAPTER 21:Ethernet MAC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit6] amba_error_interrupt_mask
transmit frame corruption due to AMBA (AHB/AXI) error interrupt mask. A write to this register directly
affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be
generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit5] retry_limit_exceeded_or_late_collision_mask
A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only)
interrupt mask. A write to this register directly affects the state of the corresponding bit in the interrupt
status register, causing an interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit4] transmit_buffer_under_run_interrupt_mask
transmit buffer under run interrupt mask. A write to this register directly affects the state of the
corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit3] transmit_used_bit_read_interrupt_mask
transmit used bit read interrupt mask. A write to this register directly affects the state of the
corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit2] receive_used_bit_read_interrupt_mask
receive used bit read interrupt mask. A write to this register directly affects the state of the
corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit1] receive_complete_interrupt_mask
receive complete interrupt mask. A write to this register directly affects the state of the corresponding bit
in the interrupt status register, causing an interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
Summary of Contents for S6J3200 Series
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