Cypress S6J3200 Series, Manual

Page: 445 / 1355

CHAPTER 18:Sound Generator
444 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.1.
DMA Transfer Update Enable Register (SGDER)
The DMA Transfer Update Enable Register (SGDER) is to enable the update of the registers (SGAR,
SGFR, SGNR, SGTCR, SGIDR, SGPCR) which can be updated when in DMA transfer.
This setting is made for respective registers.
The Sound Generator identifies the register to be updated by DMA transfer according to the setting of this
register.
It also recognizes the number of times of DMA transfer and the transfer byte size according to the setting
of this register, as well as the valid byte position of the DMA Transfer Intermediate Register (SGDMAR).
bit 7 6 5 4 3 2 1 0
Field ARE1 ARE0 FRE NRE TCRE IDRE PCRE1 PCRE0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit7] ARE1 : Amplitude data (upper byte) update enable bit
This bit is to enable the update of the amplitude data (upper byte) of the Amplitude Data Register
(SGAR) through the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the amplitude data (upper byte) is disabled.
1 The update of the amplitude data (upper byte) is enabled.
[bit6] ARE0 : Amplitude data (lower byte) update enable bit
This bit is to enable the update of the amplitude data (lower byte) of the Amplitude Data Register
(SGAR) through the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the amplitude data (lower byte) is disabled.
1 The update of the amplitude data (lower byte) is enabled.
[bit5] FRE : Frequency data update enable bit
This bit is to enable the update of the frequency data of the Frequency Data Register (SGFR) through
the DMA Transfer Intermediate Register when in DMA transfer.
Bit Description
0 The update of the frequency data is disabled.
1 The update of the frequency data is enabled.