Cypress S6J3200 Series, Manual, Page: 941 / 1355

CHAPTER 24:Inter-IC Sound (I2S)
940 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.7.
Operation Control Register (I2Sn_OPRREG)
The Operation Control Register (I2Sn_OPRREG) controls receive and transmit operation.
Operation Control Register (I2Sn_OPRREG)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME read0 read0 read0 read0 read0 read0 read0 RXENB
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME read0 read0 read0 read0 read0 read0 read0 TXENB
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME read0 read0 read0 read0 read0 read0 read0 read0
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME read0 read0 read0 read0 read0 read0 read0 START
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:25] read0 : -
[bit24] RXENB : Receive Enable
Enable/disable functions of receiving operation is set.
Bit Description
0
Receiving operation is disabled
Reception FIFO becomes empty with writing "0" to this bit.
When RXENB is "0", the data received from serial reception bus is not written to reception FIFO.
DMA reception channel stops during DMA transfer.
1 Receiving operation is enabled
[bit23:17] read0 : -