Cypress S6J3200 Series, Manual

Page: 1009 / 1355

CHAPTER 27:HyperBus Interface
1008 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.
Operation of the HYPERBUSI
This section describes the operation of HYPERBUSI module.
3.1.
HyperBus Core
This section describes physical interface of HYPERBUSI module. The HyperBus core generates
HyperBus timing from control signals.
3.1.1.
Read Operation
This section describes the read operation of HYPERBUSI. HYPERBUSI module asserts CSn, CK, and
DQ. Then, it outputs 3 words command/address, and reads 1 or more data by the timing of RWDS.
If both RX FIFO and R DAT FIFO become full, HyperBus Core ends the access. Then, when only RX
FIFO becomes empty, HyperBus Core re-initiates the access. At this time, R DAT FIFO is transferring
read data continuously to AXI bus.
The HYPERBUSI puts the transaction request from AXI bus, such as the burst type and the burst length,
to the C/A cycle on HyperBus as is.
Figure 3-1 Read Waveform
CA0
47-40
CA0
39-32
CA1
31-24
CA1
23-16
CA0
15-8 CA0
7-0
Dn
7-0
Dn
15-8
Dn+1
7-0
Dn+1
15-8
CSn
CK
RWDS
DQ[7:0]
When device settings is 5 clocks latency
3.1.2.
Write Operation
This section describes the write operation of HYPERBUSI for HyperFlash. HYPERBUSI asserts CSn, CK,
and DQ. Then, it outputs 3 words command/address, and writes 1 or more data. This write operation is
used when the DEVTYPE of HYPERBUSI_MCRn is chosen as HyperFlash.
The HYPERBUSI module puts the transaction request from AXI bus, such as the burst type and the burst
length, to the C/A cycle on HyperBus as is.
Notes:
−
Since HyperFlash supports only the write operation in every 2bytes, invalid data (0xFF) is written
as insufficient one byte if only one byte is written.
−
When using HyperFlash, the burst write of HyperFlash is supported only when CK frequency is
50MHz or less. Therefore, when the CK frequency of HyperFlash is 50MHz or more, the write
data size in an AXI transaction should be only 2 bytes.