CHAPTER 24:Inter-IC Sound (I2S)
912
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Transfer Setting
Operation
Master Mode (I2Sn_CNTREG:MSMD = "1")
Slave Mode (I2Sn_CNTREG:MSMD = "0")
Transmission only
I2Sn_CNTREG:
TXDIS = "0"
I2Sn_CNTREG:
RXDIS = "1"
Stop
At the time of stop, transmission FIFO becomes
empty when there’s no data transfer from internal
memory to I2S transmission FIFO.
To maintain I2Sn_OPRREG:START bit to "1":
I2Sn_OPRREG:TXENB = "1":
When "1" is written to I2Sn_OPRREG:TXENB,
synchronous signal is output in the free-running
mode. When transmission FIFO becomes empty,
empty frame is output.
In burst mode, frame synchronous signal is not
output, and empty frame bits are output to serial
data bus.
I2Sn_OPRREG:TXENB = "0":
When "0" is written to I2Sn_OPRREG:TXENB,
transmission FIFO becomes empty. In the
free-running mode, frame synchronous signal
continues outputting and serial bus becomes high
impedance state. In the burst mode, frame
synchronous signal is not output and serial data
bus becomes high impedance state.
To make I2Sn_OPRREG:START bit "0":
When "0" is written to I2Sn_OPRREG:START bit,
then transmission FIFO becomes empty. Clock
supply to the serial control part is stopped
regardless of I2Sn_OPRREG:TXENB setting.
Serial Output Clock and Frame synchronous signal
output is stopped. Serial data bus becomes high
impedance state.
To maintain I2Sn_OPRREG:START bit to
"1":
I2Sn_OPRREG:TXENB = "1":
Empty frame data is output to serial bus.
I2Sn_OPRREG:TXENB = "0":
When "0" is written to I2Sn_OPRREG:TXENB,
transmission FIFO becomes empty, and data
present in the transmission FIFO at the time "0"
was written to I2Sn_OPRREG:TXENB is not
transmitted.
Writing to transmission FIFO and detection of
the frame synchronous signal are stopped.
Serial data bus becomes high impedance state.
To make I2Sn_OPRREG:START bit "0":
When "0" is written to I2Sn_OPRREG:START
bit, transmission FIFO becomes empty. Writing
to transmission FIFO and detection of frame
synchronous signal are stopped regardless of
I2Sn_OPRREG:TXENB setting and serial bus
becomes high impedance state.
Abnormality
When reading from transmission FIFO occurs
while it is empty, empty frame is output. For the
setting conditions of I2Sn_STATUS:TXUDR0 and
I2Sn_STATUS:TXUDR1, refer to their bit
descriptions.
When writing to transmission FIFO occurs while it
is full, set I2Sn_STATUS:TXOVR to "1".
When reading from transmission FIFO occurs
while it is empty, empty frame is output. For the
setting conditions of I2Sn_STATUS:TXUDR0
and I2Sn_STATUS:TXUDR1, refer to their bit
descriptions. However
I2Sn_STATUS:TXUDR0/1 are not set to "1" for
the 1st output frame after the bits become
I2Sn_OPRREG:START = "1" and
I2Sn_OPRREG:TXENB = "1".
When writing to transmission FIFO occurs while
it is full, I2Sn_STATUS:TXOVR is set to "1". If
the frame synchronous signal is not input with
the defined frame rate in the free-running
mode, I2Sn_STATUS:FERR is set to "1".
If the next frame synchronous signal is input
before completing 1 frame
transmission in the burst mode,
I2Sn_STATUS:FERR is set to "1".
Summary of Contents for S6J3200 Series
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