Cypress S6J3200 Series, Manual

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CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 437
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Decrement counter is 0x00
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At the rising edge of SGO
(9) DMAC clears the interrupt, and write registers in the Sound Generator through the "DMA Transfer
Intermediate Register (SGDMAR)".
(*2: DMA block size must to be "4-byte size x 2" for the access to "DMA Transfer Intermediate Register
(SGDMAR)")
(10) The Sound Generator keeps outputting SGO and SGA, according to the register settings above.
(11) When DMAC completes all DMA transfer (with 4-byte size x2, N times), it asserts an interrupt to
MCU.
(12) Software makes settings to those registers which are needed in DMA transfer. The DMA transfer is
based on a block data of "2-byte size x 1", and this block can be repeated M times. DMAC sets following
registers to prepare for a DMA transfer, through the "DMA Transfer Intermediate Register (SGDMAR)".
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Frequency Data Register (SGFR)
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Tone Output Number Register (SGNR)
The destination address of the DMA transfer is a fixed one on the "DMA Transfer Intermediate Register
(SGDMAR)".
(13) Software configures the "DMA Transfer Update Enable Register (SGDER)" to enable the automatic
update of the following registers during DMA transfer.
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Frequency Data Register (SGFR)
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Tone Output Number Register (SGNR)
(14) The Tone pulse counter counts the number of tone pulses. When the following conditions are
satisfied, the interrupt is generated.
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Tone pulse counter is 0x00
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Decrement counter is 0x00
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At the rising edge of SGO
(15) DMAC clears the interrupt, and write registers in the Sound Generator through the "DMA Transfer
Intermediate Register (SGDMAR)".
(*3: DMA block size must to be "2-byte size x 1" for the access to "DMA Transfer Intermediate Register
(SGDMAR)")
(16) Repeat the flow from 14 to 15 to continue outputting the sound.
(17) When DMAC completes all DMA transfer (with 2-byte size x1, M times), it asserts an interrupt to
MCU.
(18) Software writes "0" to the Start bit (SGCR.ST) to stop outputting the sound.
(19) When above operation (18) was made within the following time, the Mth DMA transfer doesn't come
to the output of SGO and SGA. The Sound Generator stops driving SGO and SGA just before outputting
the data of Nth DMA transfer.
The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle
(*4: The data of the Mth DMA transfer are written to the Sound Generator, however, they are not output.
DMAC issues this Mth DMA transfer only to assert an interrupt toward the MCU.)
(20) If above (19) is not done within the limit time, the Sound Generator keeps driving SGO and SGA in
order to output the data of the Mth DMA transfer. Then, the Sound Generator stops driving SGO and SGA
after the end of all data.
(*4: The data of the Mth DMA transfer are written to the Sound Generator, and they are output to the end.)