Cypress S6J3200 Series, Manual

Page: 1237 / 1355

CHAPTER 33:Graphics Subsystem
1236 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
 dsp1_ClockDivider
REGISTER_NAME dsp1_ClockDivider
OFFSET 0x10x60
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
Clock divider register.
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME dsp1_ClockDivider[15:8]
ACCESS_TYPE R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 1 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME dsp1_ClockDivider[7:0]
ACCESS_TYPE R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 1 1 1 1 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit23:8] dsp1_ ClockDivider : display1 Clock Divider
Fixed point clock divider setting with 8 decimal places. Must be at least 2.0. Do not program in a way
that a display clock in excess of the maximum frequency that the design can handle is generated,
otherwise behavior of the silicon can be undefined. Can be written while clock is already enabled,
generated clock will adapt to the new setting then.
Unless the clock divider is an integer, there will be a mix of lower and higher clock frequencies. Maximal
peak frequency is calculated as follows.
If floating part of the DIVIDER is >= 0.5: fDSP_CLK_max = fREF_CLK / (2 x int(dsp0/1_ClockDivider) +
1)