Cypress S6J3200 Series, Manual

Page: 232 / 1355

CHAPTER 12:State Transition
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 231
Hard Reset (PONR)
VCC5
VCC53
DVCC
AVCC5
VCC3
AVCC3
VCC12
VCC3_LVDS_Tx
AVCC3_LVDS_PLL
PSC1 ON
LVDL2 Reset RESET
POR RESET
LVDH1 Reset RESET
LVDH2 Reset RESET
RSTX (optional) RESET
VCC53/VCC3 I/O Soft Reset RESET
(SYSC0_SPECFGR:IO3/35RSTC)
LVDS Soft Reset (CNTR0:PWD12/33) RESET
Internal Reset RESET
CLK_CPU Oscillation
CLK_CPU enable ON
Regulator of flash memory Reset RESET
SYSC Reset RESET
CLK_SYSC0H Oscillation
CPU operating ON
VCC12 domain(PD2) state ON
(9) BootROM
program operating
(10) User
program operating
(11) User
program operating
(LVDS & VCC3/53
I/O soft reset
released by register
access)
processing description
(1) VCC5
AVCC5
power-on
(2) VCC3
AVCC3
(3.3V supplies)
power-on
VCC53
DVCC
(5V supplies)
power-on
(can be switched on
as soon as
Vcc5/AVCC5 are >
4.5V)
(3) Int-Regulator
stabilization wait
and
Power On Reset
release
(4) Fast/Slow-CR
stabilization wait
(Fast-CR*1920cycle)
(5) VCC12 turned on
by PSC1="H" and
LVDL2 reset asserted
until VCC12 rises
above release
threshold
(6) VCC12 Voltage
stabilization wait by
counter
(Configurable by bit
SYSC0_SPECFGR:EX
12VRSTCNT.
Internal reset is
released after the wait
period of
14.2ms~33.3ms from
LVDL2 reset release)
(7) Regulator of flash
stabilization wait
(VCC3_LVDS_Tx
and
AVCC3_LVDS_PLL
power can be
enabled as soon as
Vcc12 is stable)
(8) Mode evaluation
and
Security evaluation
and
Internal reset release
(Fast-CR*8cycle)
Below table describes reset asserted until stabilization of each supply.
# Power supply Reset
Who must
monitor the
supply?
Corresponding
phase in POR
release diagram
(Figure3-1)
1
VCC5
LVDH1 reset CY MCU (1)
2 VDD (internal 1.2V) POR CY MCU (3)
3 VCC53 LVDH1 reset or RSTX CY MCU (1) or (2)
4 DVCC LVDH1 reset or RSTX
CY MCU or
User
(1)
5 AVCC5 LVDH1 reset or RSTX
CY MCU or
User
(1)
6 VCC3 RSTX User (2)
7 AVCC3 RSTX User (2)
8 VCC12
Internal power
controller reset
User (6)
9 AVCC3_LVDS_PLL NA User (11)
10
VCC3_LVDS_TX
NA User (11)
Ensure use of LVDS after this supply is stable by software.
LVDH1 can monitor AVCC5 only if it's shorted with VCC5 on the
board. Otherwise, this supply has to be monitored on the board
and RSTX has to be issued to inactivate the domain until the
supply is stable.
Explanation of Reset
VCC5 is monitored by LVDH1 which issues & releases reset
above minimum operation voltage
VDD rises above minimum operation voltage during Int-
Regulator stabilization wait shown in (3) in sheet POR Diagram
LVDH1 can monitor VCC53 only if it's shorted with VCC5 on the
board. Otherwise, this supply has to be monitored on the board
and RSTX has to be issued to inactivate the domain until the
supply is stable.
LVDH1 can monitor DVCC only if it's shorted with VCC5 on the
board. Otherwise, this supply has to be monitored on the board
and RSTX has to be issued to inactivate the domain until the
supply is stable.
This supply has to be monitored on the board and RSTX has to
be issued to inactivate the domain until the supply is stable.
This supply has to be monitored on the board and RSTX has to
be issued to inactivate the domain until the supply is stable.
This reset is released after VCC12 stabilization counter expires
(14.2ms~33.3ms). VCC12 has to rise above safe level within
14.2ms~33.3ms after LVDL2 reset release.
Ensure use of LVDS after this supply is stable by software.
3.
Fetching the Operation Mode
This section describes the Fetching the Operation Mode.
The operation mode is fetched by sampling the RST (Reset).
The following shows an operation sequence from an occurrence of reset cause to the determination of an
operation mode.
Figure3-1 Operation Mode Fetch Timing Chart