CHAPTER 21:Ethernet MAC
680
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit7:0] vector_enable: Priority vector enable
If bit 17 of the Network Control register is written with a "1" then the priority enable vector of the PFC
priority based pause frame will be set equal to the value stored in this register [7:0].
Summary of Contents for S6J3200 Series
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