CHAPTER 18:Sound Generator
428
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
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Decrement counter is 0x00
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At the rising edge of SGO
(9) DMAC clears the interrupt, and write registers in the Sound Generator through the "DMA Transfer
Intermediate Register (SGDMAR)".
(*2: DMA block size must to be "4-byte size x 2" for the access to "DMA Transfer Intermediate Register
(SGDMAR)")
(10) The Sound Generator keeps outputting SGO and SGA, according to the register settings above.
(11) The Tone pulse counter counts the number of tone pulses. When the following conditions are
satisfied, the interrupt is generated.
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Tone pulse counter is 0x00
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Decrement counter is 0x00
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At the rising edge of SGO
DMAC doesn't assert an interrupt to MCU until the DMAC completes all DMA transfer (with 4-byte size x2,
N times).
(12) Repeat the flow from 9 to 11 to continue outputting the sound.
(13) When DMAC completes all DMA transfer (with 4-byte size x2, N times), it asserts an interrupt to
MCU.
(14) Software writes "0" to the Start bit (SGCR.ST) to stop outputting the sound.
(15) When above operation (14) was made within the following time, the Nth DMA transfer doesn't come
to the output of SGO and SGA. The Sound Generator stops driving SGO and SGA just before outputting
the data of Nth DMA transfer.
The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle
(*3: The data of the Nth DMA transfer are written to the Sound Generator, however, they are not output.
DMAC issues this Nth DMA transfer only to assert an interrupt toward the MCU.)
(16) If above (15) is not done within the limit time, the Sound Generator keeps driving SGO and SGA in
order to output the data of the Nth DMA transfer. Then, the Sound Generator stops driving SGO and SGA
after the end of all data.
(*3: The data of the Nth DMA transfer are written to the Sound Generator, and they are output to the end.)
Notes:
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The DMAC must finish the sequence from step 5 to 6, within the following time.
The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle
−
The DMA transfer error means the occurrence of delay in the sound data setting. It causes
unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish
all data transfer within the limit time.
Summary of Contents for S6J3200 Series
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