Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
778 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.115.
Design Configuration 10 Register
(ETHERNETn_designcfg_debug10)
Description of Design Configuration 10 register is shown.
REGISTER_NAME ETHERNETn_designcfg_debug10
OFFSET 0x2A4
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME emac_bus_width tx_pbuf_data
ACCESS_TYPE R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x2 0x2
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME rx_pbuf_data axi_access_pipeline_bits
ACCESS_TYPE R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x2 0x4
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME axi_tx_desc_rd_buff_bits axi_rx_desc_rd_buff_bits
ACCESS_TYPE R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x4 0x4
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME axi_tx_desc_wr_buff_bits axi_rx_desc_wr_buff_bits
ACCESS_TYPE R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x4 0x4
[bit31:28] emac_bus_width:
Takes the value of `gem_ emac_bus_width. Writing has no effect.
[bit27:24] tx_pbuf_data:
Takes the value of `gem_ tx_pbuf_data. Writing has no effect.
[bit23:20] rx_pbuf_data:
Takes the value of `gem_ rx_pbuf_data. Writing has no effect.