Cypress S6J3200 Series, Manual

Page: 1339 / 1355

CHAPTER 37:Major Changes
1338 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
Polarity of
RSTX is
wrong
238 - 262 (RSTX pin level in figure is changed) #353
PSC pin state
during serial
writer mode
243 - 267
6.1. PSC port statePSC port which is
expected to control switching of external
power supply devises will output "low"
during external reset ("low" is inputted to
RSTX) in SERIAL PROGRAMMING
MODE. After reset ("high" is inputted to
RSTX), PSC port will output "high". If 1.2V
power supply is supervised and RSTX is
controlled with its low voltage state, PSC
cannot output "high", that is, external
power supply devises would not start
power supplying, and MCU cannot go to a
power-on sequence before a serial
programming operation.
#153
Add the
section
"3.Operation"
and
"4.Registers"
556 - 581
3. Operation of the Ethernet MAC
4. Registers
#342
PCMPWM
DOUBLE bit
730
[bit13] DOUBLE : Double Mode Enable
This bit enables operation in mono or
stereo mode.
982
[bit13] DOUBLE : Double Mode Enable
This bit enables operation in single or
double mode.
#171
FPD-Link
internal signal
861
Notes:
− ,,,
- ,,,
1113
Notes:
−
,,,
- ,,,
−
DLYDn (n=0, 1, 2, 3, and 4), FRSEL,
RSEL, and VRM are internal signal
names which cannot be configured by
software.
#341
Error in
desctiption for
UNLOCK
register
865
Writing any value other than LOCK results
in LOCK.
1118
Writing any value other than UNLOCK
code results in LOCK.
#279
FPD-Link port
status
868
[bit16] PWD12
0:Operation
1:Power Down(default) Differential 0
output
,,,
[bit0] RST
0:Release operation
1:Reset(default)
1121
[bit16] PWD12
0:Operation
1:Power Down(default) Differential Hi-Z
output
,,,
[bit0] RST
0:Release operation
1:Reset(default) Differential 0 output
#344