CHAPTER 31:Memory Protection Unit for AXI
1148
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bit Position
Bit Field Name
Bit Description
[12]
PROT
Privilege Attribute
When privileged mode overwrite feature is available and also
MPUXn_CTRL0:POEN = "1", privilege mode attribute on AXI memory
interfaces are controlled by this bit.
"0": Non-privilege mode
"1": Privilege mode
[11]
POEN
Privileged Mode Overwrite Feature Enable
"0": Privileged mode overwrite feature is disabled "1": Privileged mode
overwrite feature is enabled
Note: For availability of privileged mode overwrite feature, refer to device
specific datasheet.
[10]
MPUSTOPEN
Enable for MPU STOP Feature
"0": MPU stop feature is disabled "1": MPU stop feature is enabled
This bit along with MPU stop input controls the STOP status of MPU AXI.
[9]
MPUSTOP
MPU Stop Status
"0": MPU AXI is not stopped
"1": MPU AXI is stopped (i.e.MPUXn_CTRL0:MPUSTOPEN = "1"
and MPU stop input is asserted). All accesses on AXI master memory write or
read address channel are converted to FIXED type burst with predefined
address
Note: For availability of MPU stop feature, refer to device specific datasheet.
[8]
LST
MPU Lock Status
"0": MPU AXI is unlocked, registers in MPU AXI can be written
"1": MPU AXI is locked, no registers (other than MPUXn_UNLOCK register)
in MPU AXI can be written
[7:2]
read0
-
[1]
NMICL
NMI Interrupt Clear "0": No effect
"1": Clears the NMI interrupt flag
Read returns "0".
[0]
NMI
NMI Interrupt Flag
This bit indicates that the memory protection violation is detected for an AXI
transaction.
Note:
−
The register bits MPUXn_CTRL0:AP, MPUXn_CTRL0:MPUSTOPEN, MPUXn_CTRL0:POEN
and MPUXn_CTRL0:PROT in MPUXn_CTRL0 register can only be written when MPU is
disabled (MPUXn_CTRL0:MPUEN = "0"). This also implies that when MPUXn_CTRL0:MPUEN =
"1":
−
32-bit or 16-bit access to this register is not allowed
−
8-bit access is required to disable the MPU
−
8-bit access is required to clear the NMI interrupt flag
Summary of Contents for S6J3200 Series
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