CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
−
Find ADC12Bn_OCV.OCV setting y for which the transition between digital values 0xFFE and
0xFFF occurs.
−
Set A/D Converter offset compensation setting register ADC12Bn_OCV to the value calculated as
"(x+y)/2 + 2".
−
Set AVRHSEL bit back to "0".
−
Set AVRLSEL bit to "1".
−
For different ADC12Bn_GCV.GCV settings trigger the multiple conversion channel, i.e. perform
AVRL voltage conversion. It is better to configure multiple conversions of AVRL and calculate
average result.
−
Find ADC12Bn_GCV.GCV setting z for which the transition between digital values 0x000 and 0x001
occurs.
−
Set A/D Converter gain compensation setting register ADC12Bn_GCV to the value calculated as "z
+ 1".
−
Set AVRLSEL and AVRHSEL bits to "0".
−
Trigger and perform further logical channel conversions (analog inputs AN to which are logical
channels mapped are converted by calibrated A/D Converter).
Summary of Contents for S6J3200 Series
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