Cypress S6J3200 Series, Manual

Page: 1139 / 1355

CHAPTER 31:Memory Protection Unit for AXI
1138 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.
Operation of the MPU AXI
This section describes the operation of MPU AXI
MPU AXI provides start address and end address for each of the eight regions. MPU AXI regions are
defined with granularity of 128 bytes.
Start address specifies the first address of the region and is specified by registers MPUXn_SADDR1 to
MPUXn_SADDR8 for region 1 to region 8 respectively. Since the region granularity is 128 bytes least
significant 7 bits of start addresses will read 0.
End addresses are specified by registers MPUXn_EADDR1 to MPUXn_EADDR8 for region 1 to region 8
respectively. Least significant 7 bits of End Address Registers are read-only bits and will always read "1".
This ensures the granularity of 128 bytes.

AXI Burst Monitoring
Bus monitor and protection logic monitors AXI master "write address channel" signals and "read address
channel" signals ("AXI master interfaces" here onwards). The transactions on AXI master interfaces are
manipulated (if required) before they are passed on to AXI memory "write address channel" signals and
"read address channel" signals ("AXI memory interfaces" here onwards).
AXI protocol supports following features
−
Separate address or control and data phases
−
Burst based transaction where only start address is issued
−
Separate write and read address/control channels
−
Separate write and read data channels
AXI master begins each burst by driving transaction control information and address of the first byte in the
transaction. As the burst transaction progresses, AXI slave calculates the addresses of subsequent
transfers in the burst. The AWLEN (write address channel signal), ARLEN (read address channel signal)
specifies the number of data transfers for a burst transaction. Each burst can be of 1 to 16 transfers long.
The AWSIZE, ARSIZE signals specifies the maximum number of data transfers in terms of bytes in each
data transfer within a burst. The AXI protocol defines FIXED, incrementing and wrapping burst types.
As the addresses are defined in separate channels than data channels MPU AXI monitors and controls
only address channels of AXI. If memory protection violation is detected entire burst transaction is
manipulated to FIXED address burst with address of predefined value.
Figure Figure 3- 1 shows timings for read address channel signals. First burst is of WRAP type for which
no memory protection violation was detected. Second burst is of INCR type for which memory protection
violation was detected and hence MPU AXI manipulates the ARBURST to FIXED type and ARADDR to
predefined value (shown as ADDR_FIX).