Cypress S6J3200 Series, Manual

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CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1197
3.1.5.
Handling Interrupts
 Interrupts from the 3D Graphics Core
Interrupt control functionality (enable, status, clear) is implemented at the host Interface block of the 3D
Graphics Core (refer to [5]).
 Interrupts from the 2D Graphics Core
Interrupt control functionality (enable, status, clear) is implemented at the common control unit of the 2D
Graphics Core (refer to [1]).
 Interrupts from DDRHSSPI Module
Interrupt control functionality (enable, status, clear) is implemented at the DDRHSSPI module (refer to
[2]).
 Interrupts from VRAM Interface
Interrupt control functionality (enable, status, clear) is implemented at the SubSysCtrl registers:
VRamInterruptEnable/Preset/Clear/Status.
 Interrupts from Bus Monitor Module
Interrupt control functionality (enable, status, clear) is implemented at the Bus Monitor registers:
MonitorInterruptEnable/Clear and ErrorType (= status).
 Interrupts from Memory Protection Units
Interrupt control functionality (enable, status, clear) is implemented at the memory protection units (refer
to [3]).
3.1.6.
Memory Protection Units ( MPU )
Refer to [3].
3.1.7.
Bus Monitor
The bus monitor can observe the transfers on the high-performance matrix and remember the first error
response it detects.
To deactivate monitoring for certain masters set their corresponding bit in register MonitorDisable to "1".
To check whether an error occurred read ErrorType and check whether it is set to NONE (no error
occurred)
or SLVERR or DECERR (error occurred). Alternatively the non-maskable interrupt event can be used.
To get the master which received the error read ErrorID. For masters that use an ID you can read the ID
used from ErrorSubID.
To clear the remembered error, so that the monitor may detect another error, write "1" to MonitorClear.