Cypress S6J3200 Series, Manual

Page: 427 / 1355

CHAPTER 18:Sound Generator
426 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.7.1.
In Case of DMA Transfer with 4-Byte Size x 2 Is Made N Times
Figure 3
-
9 Sound Generator Operation with DMA (When in DMA Transfer with 4-byte Size x 2 Is Made N Times )
External Sound
Output
SG RAM DMAC MCU
SGO, SGA output #1
Address of transfer source/destination, block transfer,
Transfer size, block size, number of transfer, etc.
Interrupt clear
Sound Control Register (SGCR)
Start
∬ ∬ ∬ ∬ ∬
SGO, SGA output #n
Interrupt
DMA Transfer Intermediate Register (SGDMAR)
[Amplitude Data, Frequency Data,
Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Time Cycle, Increase and Decrease Data,
PWM Cycle Data Register]
SGO, SGA output
#n+1
∬ ∬ ∬ ∬ ∬
4 bytes x2
DMA transfer #1
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
SGO, SGA output
#n+m
(1)
(3)
(4)
(5)
(6)
:
:
Interrupt clear
Interrupt
An interrupt is asserted when the Sound
Generator is enabled to start (SGCR:ST=
”1”)
because the DMA transfer start interrupt setting
enable bit is set to “enabled” (SGCR.DMA=”1”).
This is the first DMA transfer request.
This interrupt is asserted because the Sound
Generator outputs tone pulses to the number set
in the Time Cycle Register (SGTCR) and Tone
Output Number Register (SGNR).
(7)
:
:
SGO, SGA output
#n+m+1
Interrupt clear
Interrupt
(8)
Interrupt
Interrupt
Interrupt clear
Sound Control Register (SGCR)
Stop
SGO, SGA output
#n+m+x+1
:
:
If the current tone cycle is outputting, the SGO
and SGA output stops when the current tone cycle
output is finished.
(11)
(13)
The sound output starts because access with 4-
byte size x2 is given on the DMA Transfer
Intermediate Register (SGDMAR).
This interrupt is asserted because the Sound
Generator outputs tone pulses to the number set
in the Time Cycle Register (SGTCR) and Tone
Output Number Register (SGNR).
∬ ∬ ∬ ∬ ∬
SGO, SGA output
#n+m+x
:
:
(14)
If this period is over
“(Frequency Data [SGFR] +1) x 1 PWM cycle”
and the stop instruction is set as SGCR:ST=
”0”,
the SGO and SGA are output.
(15)
(16)
DMA Transfer Intermediate Register (SGDMAR)
[Amplitude Data, Frequency Data,
Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Time Cycle, Increase and Decrease Data,
PWM Cycle Data Register]
4 bytes x2
DMA transfer #2
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
DMA Transfer Intermediate Register (SGDMAR)
[Amplitude Data, Frequency Data,
Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Time Cycle, Increase and Decrease Data,
PWM Cycle Data Register]
4 bytes x2
DMA transfer #N-1
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
DMA Transfer Intermediate Register (SGDMAR)
[Amplitude Data, Frequency Data,
Tone Output Number Register]
DMA Transfer Intermediate Register (SGDMAR)
[Time Cycle, Increase and Decrease Data,
PWM Cycle Data Register]
4 bytes x2
DMA transfer #N
Within
(Frequency Data [SGFR] +1)
x 1 PWM cycle
(9)
(10)
*2
*1
*2
*3
(12)
DMA Transfer Update Enable Register (SGDER)
Enabling data update for {amplitude, frequency,
tone output number, time cycle, increase/decrease,
and PWM cycle}
(2)
Sound Control Register (SGCR)
- Setting and enabling of increase/decrease
- Enabling prescaler, tone and interrupt Interrupt Clear Register (SGCCR)
- Initializing interrupt