Cypress S6J3200 Series, Manual

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CHAPTER 3:Product Description
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 47
3.
Note
3.1.
Status Flag Clear
Note that the hardware operation of a write access to a register which has status flags may be later
than program operations of software. The delay results from the fact that the write accesses and their
signals are operated through multiple buses.
For example, when a software program intends to return from interrupt software routine (ISR) after
clearing the interrupt flag, the return instruction may practically be executed before the completion of
the write access as for hardware operation. That is, the CPU execution may immediately jump to the
ISR again after returning from the ISR because the flag is not cleared.
To avoid such a phenomenon, the execution of Data Memory Barrier (DMB) instruction between the
write access and the return instruction is recommended for the program. The return instruction is never
executed before the completion of DMB execution.
It should be considered that the method takes a number of execution cycles and that it may cause
some influence to application performance. For example, one time of the DMB execution is enough
after a number of continuous flag clear operations.
3.2.
Error Response
Error response is generated when access occurs to the following register and bit offset.
Function Register Bit Offset Access Error Type
12/10/8-BIT ANALOG TO DIGITAL
CONVERTER
ADC12Bn_CHSTAT0 to 63 Whole register Write(B,H,W) Bus error
ADC12Bn_CD0 to 63 Whole register Write(B,H,W) Bus error
ADC12Bn_CDONEIRQ0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_GRPIRQ0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_RCIRQ0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_PCIRQ0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_TRGST0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_RCOTF0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_TRGOR0 to 1 Whole register Write(B,H,W) Bus error
ADC12Bn_MCSTAT0 to 3 Whole register Write(B,H,W) Bus error
(Other reserved area) (Other reserved area) Read / Write(B,H,W) Bus error
Stepper Motor Controller
SMCi_PWSS bit [7:0] Reserved Write(B) Bus error
SMCi_PTRGDL bit [15:8] Reserved Write(B) Bus error
Trigger configuration of Stepper
motor controller
SMCTGg_PTRG bit [15:8] Reserved Write(B) Bus error
INTER IC SOUND (I2S)
I2Sn_RXFDAT0 to 15 Whole register Write(B,H,W) Bus error
I2Sn_OPRREG bit [15:8] Reserved Write(B) Bus error
I2Sn_SRST bit [31:8] Reserved Write(B,H) Bus error
I2Sn_STATUS bit [15:0] Write(B,H,W) Bus error
I2Sn_DMAACT
bit [31:24] Reserved
bit [15:8] Reserved
Write(B) Bus error
I2Sn_DEBUG bit [31:8] Reserved Write(B,H) Bus error
I2Sn_MIDREG Whole register Write(B,H,W) Bus error