CHAPTER 21:Ethernet MAC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit11] enable_resp_not_ok_interrupt: Enable BRESP not OK interrupt
Writing "1" enables BRESP not OK interrupt.
[bit10] enable_receive_overrun_interrupt: Enable Receive over run interrupt
Writing "1" enables Receive over run interrupt.
[bit9:8] Reserved
Always read "0". Writing has no effect.
[bit7] enable_transmit_complete_interrupt: Enable Transmit complete interrupt
Writing "1" enables Transmit complete interrupt.
[bit6] enable_transmit_frame_corruption_due_to_amba_error_interrupt: Enable
Transmit frame corruption due to AMBA AXI error interrupt
Writing "1" enables Transmit frame corruption due to AMBA AXI error interrupt.
[bit5] enable_retry_limit_exceeded_or_late_collision_interrupt: Enable Retry limit
exceeded or late collision interrupt
Writing "1" enables Retry limit exceeded or late collision interrupt.
[bit4:3] Reserved
Always read "0". Writing has no effect.
[bit2] enable_rx_used_bit_read_interrupt: Enable RX used bit read interrupt
Writing "1" enables RX used bit read interrupt.
[bit1] enable_receive_complete_interrupt: Enable Receive complete interrupt
Writing "1" enables Receive complete interrupt.
[bit0] Reserved
Always read "0". Writing has no effect.
Summary of Contents for S6J3200 Series
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