Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
580 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
transfers can be made with a single request. The burst length is controlled via the DMA Configuration
register (ETHERNETn_dma_config[4:0]).
3.1.2.
Partial Store and Forward Using Packet Buffer DMA
The Ethernet MAC can be programmed into a low latency mode, known as partial store and forward. This
allows for a reduced latency as the full packet is not buffered before forwarding. This option is only
available when not using multi buffer frames. This feature is enabled via the TX and RX Partial Store and
Forward registers (ETHERNETn_pbuf_txcutthru, ETHERNETn_pbuf_rxcutthru). When transmit partial
store and forward mode is activated, the transmitter will only begin to forward the packet to the MAC
when there is enough packet data stored in the TX Packet Buffer Memory. Likewise, when receive partial
store and forward mode is activated, the receiver will only begin to forward the packet to the system
memory when enough packet data is stored in the RX Packet Buffer Memory. The amount of packet data
required to activate the forwarding process is programmable via watermark registers which are located at
the same address as the partial store and forward enable bits. Note that the minimum operational value
for the TX partial store and forward watermark is 20. There is no operational limit for the RX partial store
and forward watermark. Enabling partial store and forward is a useful means to reduce latency, but there
are performance implications. In essence, the packet buffer DMA will start behaving in a similar way to the
internal FIFO DMA mode when partial store and forward is enabled. Information regarding this behavior is
described in section Receive DMA Buffers. When priority queuing is enabled, each TX Packet Buffer
Memory region allocated to a queue must be greater than the size of the maximum frame length to be
transmitted.
3.1.3.
Ethernet MAC DMA Transactions
The Ethernet MAC DMA uses separate transmit and receive lists of buffer descriptors, with each
descriptor describing a buffer area in system memory. This allows Ethernet packets to be broken up and
scattered around the system memory.
The Ethernet MAC DMA controller performs six types of operation on the AMBA bus. In order of priority
these are:
1. receive buffer manager write/read
2. transmit buffer manager write/read
3. receive data DMA write
4. transmit data DMA read
All read operations are routed to the AXI Master Interface read channel and all write operations to the AXI
Master Interface write channel. Both read and write channel operate simultaneously. Arbitration logic is
used when multiple requests are active on the same channel (e.g. when the TX DMA requests a transmit
data read at the same time the RX DMA requests a receive descriptor read). In these cases, the RX DMA
is granted the bus before the TX DMA. However the vast majority of requests are either receive data
writes or transmit data reads both of which can operate in parallel.
Transfer size is set to 64-bit words by default in the Network Configuration register
(ETHERNETn_network_configuration) and burst length can be programmed in the range from single
access up to 16 accesses per burst using the DMA Configuration register (ETHERNETn_dma_config).