CHAPTER 24:Inter-IC Sound (I2S)
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.5.
Caution Summary
I2Sn_MCR0REG:S0WDL, I2Sn_MCR0REG:S0CHL 1 to 6 bits are prohibited
I2Sn_MCR0REG:S1WDL, I2Sn_MCR0REG:S1CHL 1 to 6 bits are prohibited
When channel length (set to I2Sn_MCR0REG:S0CHL and I2Sn_MCR0REG:S1CHL) is longer than the
word length (set to I2Sn_MCR0REG:S0WDL and I2Sn_MCR0REG:S1WDL), remaining bits in the
channel become I2Sn_CNTREG:MSKB. Setting the channel length to shorter than the word length is
prohibited
Pulse width of one channel (I2Sn_CNTREG:FSLN = "1") is prohibited when frame length is set to one
channel by I2Sn_MCR0REG:S0CHN ="0" and I2Sn_CNTREG:SBFN = "0"
Rewrite to I2Sn_CNTREG, I2Sn_MCR0REG, I2Sn_MCR1REG, and I2Sn_MCR2REG is prohibited
after I2Sn_OPRREG:START is set
Rewrite to I2Sn_CNTREG, I2Sn_MCR0REG, I2Sn_MCR1REG, and I2Sn_MCR2REG is prohibited
while DBGE is set to "1" and the processor is in debug state
Summary of Contents for S6J3200 Series
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