Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
780 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.116.
Interrupt Status Queue i Register (ETHERNETn_int_status_qi) (i=1
to 3)
Description of Interrupt Status Queue i register is shown.
REGISTER_NAME ETHERNETn_int_status_qi
OFFSET (0x400 + ((i-1)*0x4))
ACCESS_SIZE W
MULTIPLE 1:3
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
resp_not_o
k
receive_ove
rrun
Reserved
ACCESS_TYPE R0,WX R/W R/W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x0 0 0 0x0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME
transmit_co
mplete
amba_error
retry_limit_e
xceeded_or
_late_collisi
on
Reserved
rx_used_bit
_read
receive_co
mplete
Reserved
ACCESS_TYPE R/W R/W R/W R0,WX R/W R/W R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0x0 0 0 0
[bit31:12] Reserved
Always read "0". Writing has no effect.