Cypress S6J3200 Series, Manual

Page: 347 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
346 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5.20.
A/D Channel Trigger Overrun Clear Registers
(ADC12Bn_TRGORC0 to 1)
These registers contain bits for clearing corresponding A/D channel trigger overrun flags in the
ADC12Bn_TRGOR0 to 1 registers. The 64 bits are assigned to 64 logical channels.
REGISTER_NAME ADC12Bn_TRGORCi (i = 0 to 1)
OFFSET i*4
ACCESS_SIZE B H W
MULTIPLE 0:1
NUMERIC_TYPE
-
OTHER
-
5.20.1.
A/D Channel Trigger Overrun Clear Register
(ADC12Bn_TRGORC0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME TRGORC31 TRGORC30 TRGORC29 TRGORC28 TRGORC27 TRGORC26 TRGORC25 TRGORC24
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME TRGORC23 TRGORC22 TRGORC21 TRGORC20 TRGORC19 TRGORC18 TRGORC17 TRGORC16
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME TRGORC15 TRGORC14 TRGORC13 TRGORC12 TRGORC11 TRGORC10 TRGORC9 TRGORC8
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME TRGORC7 TRGORC6 TRGORC5 TRGORC4 TRGORC3 TRGORC2 TRGORC1 TRGORC0
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] TRGORC31 to 0 : Trigger Overrun Clear bits
Bit Description
0 No effect.
1 Trigger overrun flag is cleared.
When this bit is set to "1", the corresponding bit in the ADC12Bn_TRGOR0 register is cleared.